A VHDL Implementation of UART Design with BIST Capability

Abstract

The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have no choice but to accept new responsibilities that had been performed by groups of technicians in the previous years. Design engineers who do not design systems with full testability in mind open themselves to the increased possibility of product failures and missed market opportunities. BIST is a design technique that allows a circuit to test itself. In this paper, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive of the hardware overhead produced by the additional BIST circuit. The technique can provide shorter test time compared to an externally applied test and allows the use of low-cost test equipment during all stages of production.